The present invention relates to a semiconductor device and a method of manufacturing the same, for example, to a semiconductor device having fine bit lines and a method of manufacturing the same.
A plurality of fine elements constituting a semiconductor device tends to be increasingly multilayered to overlap with each other in a plan view due to high integration and miniaturization. With the multilayering of semiconductor devices, there is often used a technique in which a gate electrode of a transistor formed over a surface of a semiconductor substrate and a layer higher than the transistor are electrically coupled by a coupling layer called a plug and a conductive layer called a contact.
Furthermore, a region in which the contact can be formed, for example, a region between a pair of bit lines adjacent to each other with a gap therebetween, becomes narrow due to high integration and miniaturization. Therefore, when the region in which the contact is formed is shifted from a desired position, there is a probability that the shifted contact and a bit line adjacent to the contact cause a short circuit.
In order to prevent such a problem, an opening for forming the contact is increasingly formed by a technique called self-alignment that makes use of a difference in etching selectivity between materials of thin films to be formed instead of a conventional normal photolithography technique. The technique that forms the opening by the self-alignment is disclosed in, for example, Japanese Patent Laid-Open No. 2012-54342 (Patent Document 1), Japanese Patent Laid-Open No. 2010-40538 (Patent Document 2), and Japanese Patent Laid-Open No. 2011-77539 (Patent Document 3).